The invention relates to a semiconductor memory with column gates, and more particularly, to a semiconductor memory with a write mask function and a method of controlling a column gate during a write mask operation.
Address multiplexing is used to read and write data from or to a conventional dynamic random access memory (DRAM). The address multiplexing uses a row address strobe (RAS) signal, a column address strobe (CAS) signal and an address including row and column addresses. The DRAM includes a RAS and a CAS circuit. The RAS circuit is activated upon receiving a row address in accordance with the RAS signal, while the CAS circuit is activated upon receiving a column address in accordance with the CAS signal. When the RAS circuit is activated, a sense-amp becomes operative and remains operative until it receives a precharge command.
Referring to FIG. 1, a first example of a conventional DRAM 200 will be described. The DRAM 200 comprises a plurality of memory cells 110 (only one is shown), a plurality word lines WL, a plurality of bit line pairs BL, /BL, a sense-amp 100, column gates 101, 102 and a write amp 112. Each memory cell 110 is connected to one of the plurality of word lines WL and either one of the plurality of bit line pairs BL, /BL. The column gates 101, 102 each comprise an N-channel MOS transistor connected to the bit line BL or /BL. Each of the column gates 101, 102 has a gate which receives a column select signal CL. The bit lines BL, /BL are connected via the column gates 101, 102 to data buses DB, /DB. Both RAS and CAS circuits, not shown, are connected to the word line WL and the column select signal CL. The write-amp 112 is connected to the data buses DB, /DB.
The sense-amp 100 is connected across the bit lines BL, /BL and amplifies a potential difference thereacross when activated. The sense-amp 100 comprises P-channel MOS transistors Tr1, Tr3 and N-channel MOS transistors Tr2, Tr4. The transistors Tr1, Tr3 have their sources connected to an activation source V.sub.SAH, and transistors Tr2, Tr4 have their sources connected to an activation source V.sub.SAL. When the activation source V.sub.SAH, assumes a high level and the activation source V.sub.SAL assumes a low level, the sense-amp 100 is activated. In contrast, when both of the sources V.sub.SAH, and V.sub.SAL assume the same level, the sense-amp 100 is deactivated.
When reading data from the memory cell 110, the RAS circuit is initially activated, and a particular word line WL is selected. Data from the memory cell 110 connected to the word line WL is read onto the bit lines BL, /BL, and is then amplified by the sense-amp 100. Then follows the activation of the CAS circuit, which turns on the column gates 101, 102 connected via the column select signal CL. In response thereto, the bit lines BL, /BL are connected to the data buses DB, /DB, respectively, thus providing data on the bit lines BL, /BL to the data buses DB, /DB, respectively. When the column gates 101, 102 are turned on, a load on the sense-amp 100 increases. This load variation disturbs the data on the bit line BL, as indicated by phantom lines in FIG. 2. The disturbance disappears in response to the falling edge of the column select signal CL which turns off the column gates 101, 102. Subsequently, the sense-amp 100 is precharged in response to a precharge command. Because the precharge takes place after the disappearance of the disturbances, the occurrence of disturbances presents no problem to the data read operation.
During a write operation, the word line WL is selected before the column gates 101, 102 are turned on. The write-amp 112 feeds data to be written via the data buses DB, /DB and the column gates 101, 102 onto the bit lines BL, /BL, and into the memory cell 110. If disturbances to the data on the bit lines BL, /BL now occur, the strong drive of the data to be written by the write-amp 112 avoids any problem associated with the occurrence of disturbances.
Referring to FIG. 3, a second example of a conventional DRAM 210 which is a direct sensing type will be described. The direct sensing type DRAM 210 uses a technique of rapidly delivering data from a sense-amp to a peripheral circuit. In addition to the components shown in FIG. 1 for the DRAM 200, the DRAM 210 includes write column gates 103, 104, read data detecting NMOS transistors 105, 106 and a control transistor 107.
The column gates 103, 104 are each formed by N-channel MOS transistors connected in series with the column gates 101, 102, respectively. The column gate transistors 103, 104 have respective gates which are connected to a write column line WCL. NMOS transistors 105, 106 have gates which are connected to the bit lines BL, /BL, respectively. The MOS transistor 105 has a drain connected to the data bus /DB and a source connected to the N-channel MOS transistor 107. The MOS transistor 106 has a drain connected to the data bus DB and a source connected to the NMOS transistor 107. The column gates 101, 102 and the MOS transistor 107 receive a column select signal CL0 at their respective gates.
During a read operation, the MOS transistors 105, 106 detect the levels of the bit lines BL, /BL, respectively, when the column gates 101, 102 and the MOS transistor 107 are turned on. When the bit line BL assumes an H level and the bit line /BL assumes an L level, the MOS transistor 105 is turned on and the MOS transistor 106 is turned off. In response to the turn-on of the MOS transistor 105, an L level is set on the data bus /DB, and in response to the turn-off of the MOS transistor 106, an H level is set up on the data bus DB. In this manner, data on the bit lines BL, /BL are read on the data buses DB, /DB.
During a write operation, the column gates 101, 102 and the write column gates 103, 104 are turned on. The write-amp 112 amplifies data to be written and transmits it to the data buses DB, /DB. The amplified data are fed via the column gates 101, 102 and the write column gates 103, 104 to the bit lines BL, /BL to be written into a selected memory cell 110.
The DRAM 210 also performs a write mask operation, which is a type of write operation. A write mask operation enables a write operation only to a desired bit line or lines. In other words, during the write mask operation, a certain bit line or lines to which no data write operation should take place are masked to prevent a write operation thereto.
Specifically, during the write mask operation, both of the data buses DB, /DB are held at an H level, thus inhibiting the operation of the write-amp 112. Under this condition, the column gates 101, 102 and the write column gates 103, 104 are turned on to establish a connection between the data buses DB, /DB and the bit lines BL, /BL. At this time, the sense-amp 100 amplifies data from the memory cell 110 which is selected by the word line WL and rewrites this data into the memory cell 110, without being influenced by the data from the data buses DB, /DB. The data write operation is inhibited in this manner by disabling the operation of the write-amp 112.
A DRAM drive technique has been proposed in which a command and an address are collectively received as an input and a single command covers an active phase to a precharge phase of a sense-amp. This technique is particularly preferred for use in a read operation of a direct sensing type DRAM.
During a read operation, the sense-amp 100 passes data on the bit lines BL, /BL to the data buses DB, /DB via the MOS transistors 105, 106, and accordingly, there is no variation in the load on the sense-amp 100. Consequently, as illustrated in FIG. 4, there is no disturbance to the data on the bit lines BL, /BL. This allows the sense-amp 100 to be transferred from the active condition to the precharge operation anytime.
However, during a write operation, the load on the sense-amp 100 increases in response to the turn-on of the column gates 101 to 104. As a consequence, the data which is passed from the data buses DB, /DB to the bit lines BL, /BL is subject to disturbances as shown in phantom lines in FIG. 4. These disturbances are of no particular consequence for the normal write operation, since at that time a strong drive is provided to the data on the bit lines BL, /BL by the write-amp 112. Specifically, the write-amp 112 operates to increase the difference between the data levels on the bit lines BL, /BL, eliminating any adverse influence of disturbances.
However, the load variation causes a problem during the write mask operation. A load on the sense-amp 100 increases in response to the turning-on the column gates 101 to 104 during the write mask operation as well as above write mode. And the disturbance on the bit line BL occurs. In the write mask operation, the write-amp 112 does not operate, therefore, the sense-amp 100 amplifies the voltage between the bit line pair BL, /BL, to remove the disturbance. However, a drive ability of the sense-amp 100 is smaller than that of the write-amp, therefore, it takes a relatively long time to remove the disturbance. In addition, in new types of devices, such as First Cycle RAM (FCRAM), an active period of sense-amp is shorter than conventional type memory devices.
If the sense-amp 100 completes its rewriting into the memory cell 110 and enters the precharge operation before the disturbance is removed (FIG. 4), a malfunction is caused. In other words, a write into the memory cell 110 takes place before the ground level has not been recovered on the bit line BL.
It is an object of the invention to provide a semiconductor memory which accurately executes a write mask operation.